In general, a level shifter changes a level of operation power used for a memory circuit, and more specifically the level shifter typically shifts the level of internal voltage from a lower level to a higher level.
FIG. 1 is a circuit diagram illustrating a level shifter according to the related art.
As illustrated in FIG. 1, the level shifter according to the prior art shifts an input signal Vin at a low voltage level (B power) into a signal Vout at a high voltage level (A Power) and then outputs the signal Vout.
For example, when the input signal Vin is high, a node C becomes low, so that an NMOS transistor N2 is turned off. However, a node D becomes high, so that an NMOS transistor N4 is turned on.
As the NMOS transistor N4 is turned on, a node B becomes low, so that an inverter INV2 outputs a high output signal Vout at a high voltage level (A Power).
Meanwhile, a semiconductor memory turns off most internal powers to reduce the amount of consumed current in a deep power down mode. Hereinafter, an operation of the level shifter of FIG. 1 in the deep power down mode will be described as follows.
For example, when an internal power (B power) is turned off in the deep power down mode, the inverters INV1 and INV3 and the NMOS transistors N1 and N2, which use the B power, do not operate, so that the nodes C and D are floated. In detail, the nodes C and D are maintained in an unclear logic level state.
Thus, the nodes A and B are maintained in an unclear logic level state, so that electric current from the A power may flow into the ground through the PMOS transistors P1 and P2 and the NMOS transistors N3 and N4.